1. Field of the Invention
The present invention relates to a frame synchronizing circuit for discriminating the time slot location of each channel of a time-division multiplex signal and, more particularly, a frame synchronizing circuit which processes a time-division multiplexed signal in parallel.
2. Description of the Related Art
In time-division multiplexing, the signals (pulses) of respective channels to be multiplexed are allocated continuously to time slots, one after another, and pulses forming a frame synchronizing pattern are inserted periodically. The period for inserting the frame synchronizing pattern is called a frame. On the receiving side, a received pulse train is checked once each frame and the time slot location of each channel is discriminated by detecting the frame synchronizing pattern. This is called frame synchronization.
Frame synchronization is generally required to satisfy the following important factors.
(1) Synchronization should be established as quickly as possible (high speed recovery from asynchronization);
(2) Once synchronization is established, misframing, caused by a momentary change of the frame synchronizing pattern due to code or transmission error which is interpreted as asynchronization, should be minimized (forward guard); and
(3) Asynchronization should not be interpreted as synchronization (backward guard).
One frame synchronization recovery method is the one bit shift method. In this method, the frame counter in the receiving side is stopped for one bit for each detection of noncoincidence of the frame synchronizing pattern and synchronization recovery is carried out by shifting bit by bit the relative phase of the frame pulse in the input signal and the frame pulse generated in the receiving side.
The one-bit immediate shift method has also been proposed. In this method, when noncoincidence of the frame synchronizing pattern is detected, the counter system of the synchronizing circuit is immediately stopped for one time slot to shift one-bit and simultaneously "next detection" is carried out.
A synchronization guarding circuit is typically included in the frame synchronizing circuit to reduce the risk of generating a misframe due to code error (the forward guarding function). However, such synchronization guarding circuit increases the detecting time for actual asynchronization. Meanwhile, the backward guarding function reduces the likelihood of mistaking asynchronization for synchronization, but increases the possibility of rejecting synchronization. Thus, design of a synchronization guarding circuit requires the trade off of contradictory factors.
A conventional one-bit immediate shift type frame synchronizing circuit, which performs frame synchronization recovery processing, has a limitation in that the one-bit immediate shift is impossible if loop delay is not suppressed within one time slot. Therefore, if the number of multiplexed channels is increased, such as in an optical communication system, high speed signal processing is required because the signal bit rate rises as high as 405 Mbps, 565 Mbps or 810 Mbps. At this rate, it is impossible for an ordinary device to perform frame synchronization.
In addition, it is desirable to use a complementary metal oxide semiconductor integrated circuits (CMOS-ICs) because CMOS-ICs consume less power. However, CMOS-ICs have an operation rate limit of about 30 Mbps and therefore cannot be employed for a multiplexed signal of about 45 Mbps which is standard in North America. As a result, a transistor-transistor logic integrated circuit (TTL-IC) which consumes a relatively large amount of power is used instead of a CMOS-IC.
Due to the above-described problems, recently a parallel frame synchronizing circuit has been proposed where the bit rate is reduced by one-half. In such a circuit, the frequency of the high order group digital multiplexed signal is separated into two signal trains. In such a parallel frame synchronizing circuit, it is possible to suppress loop delay in the circuit within one time slot because the bit rate is reduced. However, since the frame synchronizing pattern is separated into two partial patterns, the bit length of the frame synchronization pattern is reduced by one-half. In general, when the bit length of the frame synchronization pattern is shortened, the number of forward protection stages and backward protection stages of the synchronization guarding circuit must be increased and the resultant time required for synchronization recovery becomes longer. Accordingly, where a frame synchronization pattern with the same length as the ordinary pattern is used in such a parallel frame synchronizing circuit, there is a disadvantage in that the synchronization recovery time is longer than in an ordinary frame synchronizing circuit.